Job Description

As a Sr. Principal DSP Architect, you will join a team of DSP/Systems experts, digital designers, and mixed-signal design engineers developing advanced DSP SerDes for next generation 400G per lane wireline and optical interconnect for AI systems. The DSP architecture team is responsible for research, algorithm creation, hardware/firmware implementation, post-silicon optimization, and test plan guidance.

Responsibilities

• Research novel modulation, equalization, and FEC techniques for 400G per lane wireline and optical systems
• Create DSP and FEC algorithms, bit/cycle accurate C/C++ models, and hardware block specifications appropriate for RTL implementation
• Work with digital team/firmware team to optimize and implement DSP algorithms in hardware/firmware
• Hands-on involvement in post-silicon performance tuning and optimization
• Provide guidance on test plans for lab characterization
• Provide support for internal customers deploying SerDes IP

Requirements

• Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 5-10 years of experience with DSP architectures and algorithm development
• Solid understanding of and experience with designing adaptive DSP algorithms
• Solid understanding of and experience with the practical aspects of digital communication and signal processing theory, including channel equalization, timing recovery, detection, and estimation
• Good programming skills in C/C++, Matlab or Python
• Experience in guiding and testing the transfer of high-speed numerical algorithms from C/C++ to Verilog

Benefits

• No benefits