Job Description

Samsung Semiconductor is seeking an experienced Senior Staff Engineer for their Logic Pathfinding Lab in San Jose. The role involves researching and evaluating advanced technology options through design/system-technology optimization (DTCO) for sub-2nm technology nodes, including standard cell architecture creation, library characterizations, and process design kit (PDK) generation.

Responsibilities

• Create and optimize standard cell architecture and libraries for PPAC assessment
• Optimize DTCO collaterals for block-level design
• Analyze technology design rules and process capabilities
• Develop early DTCO methodologies
• Develop internal benchmarking capability
• Collaborate and guide external vendors on DTCO development

Requirements

• PhD in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science and Engineering, Computer Science, Physics or related fields
• 10+ years of industry experience
• Standard cell layout design and library generation skills
• RTL synthesis, place and route, and timing analysis skills
• DTCO modeling skills
• Understanding of power delivery network schemes

Benefits

• No benefits