Overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs.
Responsibilities
Overseeing the planning, coordination, and execution of ASIC design
Developing/maintaining timing constraints and timing signoff methodology
Driving multiple complex designs to production
Working with IP vendors for RTL and hard-macro blocks
Requirements
Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred
3+ years’ experience supporting or developing complex SoC/silicon products
Expertise in timing constraints, timing signoff methodology, and timing closure
Hands-on knowledge of synthesis, place and route, timing, extraction, formal verification, and other backend tools
Experience with Cadence and/or Synopsys physical design tools/flows